The present invention relates to nonvolatile programmable semiconductor memory that utilizes the breakdown of thin oxide as the programming mechanism, and more particularly, to a method for determining the programming viability of the thin oxide for programming.
Nonvolatile memory retains stored data when power is removed, which is desirable in many different types of electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (xe2x80x9cPROMxe2x80x9d), which uses word line xe2x80x94bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices such as the floating gate avalanche injection metal oxide semiconductor (xe2x80x9cFAMOSxe2x80x9d) transistor to store logical information.
Improvements in the various processes used for fabricating the various types of nonvolatile memory tend to lag improvements in widely used processes such as the advanced CMOS logic process. For example, processes for devices such as flash EEPROM devices tend to use 30% more mask steps than the standard advanced CMOS logic process to produce the various special regions and structures required for the high voltage generation circuits, the triple well, the floating gate, the ONO layers, and the special source and drain junctions typically found in such devices. Accordingly, processes for flash devices tend to be one or two generations behind the standard advanced CMOS logic process and about 30% more expensive on a cost-per-wafer basis. As another example, processes for antifuses must be suitable for fabricating various antifuse structures and high voltage circuits, and so also tend to be about one generation behind the standard advanced CMOS process.
Generally, great care is taken in the fabrication of the silicon dioxide layer used in metal-oxide-silicon (MOS) devices such as capacitors and transistors. The high degree of care is necessary to ensure that the silicon dioxide layer is not stressed during manufacture or subsequent normal operation of the integrated circuit, so that the desired device characteristics are attained and are stable over time. One example of how much care is taken during fabrication is disclosed in U.S. Pat. No. 5,241,200 to Kuroda, which discloses the use of a diffused layer and a shunt to discharge charges accumulated in the word line during a wafer fabrication process. Avoiding this charge accumulation ensures that a large electric field is not applied to the gate insulating film, so that variations in the characteristics of transistors using the word line as their gate wiring line and degradation and breakdown of the gate insulating film are prevented.
An example of how much care is taken in circuit design to avoid stressing the silicon dioxide layer of a transistor during normal circuit operation is disclosed in U.S. Pat. No. 6,249,472 to Tamura et al. Tamura et al. disclose an antifuse circuit having an antifuse in series with a p-channel MOS transistor in one embodiment and in series with an n-channel MOS transistor in another embodiment. While the antifuse is fabricated without the additional film manufacturing processes typically required for fabricating antifuse circuits, Tamura et al. poses another problem. When the antifuse is shorted out, the series-connected transistor is exposed to a high voltage sufficient to break down the silicon dioxide layer of the transistor. Tamura et al. disclose the addition of another transistor to the circuit to avoid exposing the first transistor to the break down potential.
The observations above generally indicate that there are still disadvantages with each of the prior art memory technologies. Even where new memory technologies are developed that traverse the disadvantages of previous memories, these new memory technologies may be slow in being adopted. One reason is that there is skepticism as to the quality of the memory cells. In particular, there is skepticism as to whether each cell can be reliably programmed.